The invention generally relates to application specific integrated circuits (ASICs), and more specifically, the invention relates to testing gate arrays.
Use of ASICs has become widespread in the semiconductor industry as giving circuit design engineers a relatively high amount of circuit functionality in a relatively small package. In particular, ASICs are customizable integrated circuits that are customized to implement a circuit specified by a design engineer (a xe2x80x9cuser-designed circuitxe2x80x9d). One type of ASIC is the gate array, which generally includes an array of function blocks, each of which are predesigned and/or prefabricated to include a particular number, arrangement, and type of semiconductor devices, e.g., transistors. To customize a gate array to implement a particular user-designed circuit specified by a design engineer, various connections are made among the semiconductor devices within the function block and/or various connections are made among function blocks (i.e., routing is customized).
ASICs, including gate arrays, once customized to implement a user-designed circuit, must be tested to ensure that the user-designed circuit operates properly. Tests must be able to detect faults, which are the results of defects (physical problems with the circuit, e.g., shorts, and/or improper circuit design), resulting in improper or unexpected circuit behavior.
Faults include xe2x80x9cStuck At Faultsxe2x80x9d (SAFs), delay faults and current faults. SAFs occur when a particular connection in the circuit remains at (is xe2x80x9cstuckxe2x80x9d at) a logical low level or a logical high level regardless of what signals are applied to the circuit. (As used herein, xe2x80x9clogical lowxe2x80x9d refers to a xe2x80x9c0xe2x80x9d signal, which is often a ground signal. A xe2x80x9clogical highxe2x80x9d refers to a xe2x80x9c1xe2x80x9d signal, which is often a VDD signal.) Delay faults occur when the circuit is designed to accommodate a particular propagation time, but the circuit actually operates much slower than expected. For instance, if a circuit was designed with the belief that there would only be a 5 ns propagation time of a signal between a first point and a second point, but in operation the signal actually takes 15 ns to propagate from the first point to the second point, the circuit may not operate properly. Current faults will often occur in circuits utilizing CMOS devices, which are not supposed to draw current when inactive, but do. The defects that cause current faults can frequently be detected by testing for SAFs.
Well-designed tests of an integrated circuit will generally be able to detect most SAFs at the gate level (i.e., the conceptual circuit design level containing Boolean logic, flip-flops, etc.) by testing all connections between logic elements. In order to test all connections between logic elements, the tester needs to be able to both (1) control, or set, the value at a particular connection and (2) be able to observe the value at the particular connection. For instance, in order to test the connection between point A and point B for Stuck At 0 faults, the tester needs to be able to apply stimulus data that ought to place a logical high on the connection line, and then the tester needs to be able to observe the connection to see if and how the value changes as a result of the stimulus data.
In discrete circuit design, the ability to control and observe a particular circuit is often done by simply probing the various connections among the logic elements of the circuit. However, with integrated circuits, the ability to probe connections internal to the circuit is generally unavailable and other methods of testing have had to be developed as a result.
One method of testing an integrated circuit that enjoys the most popularity among IC designers is xe2x80x9cscanxe2x80x9d testing, which will be described with reference to the block diagrams of FIGS. 1 and 1A. In FIG. 1, circuit 102 is generally composed of any number and arrangement of logic elements (e.g., Boolean logic gates, flip-flops, latches, etc.) and has input A and output B. Inputs A can be coupled directly to flip-flops 104 (via lines 114) or to other logic elements in logic 102. Likewise, outputs from flip-flops 104 can be coupled directly to outputs B (via lines 112), to other logic elements in logic 102, or directly to other flip-flop 104 inputs. Each flip-flop 104 contained in circuit 102 is coupled to a clock signal such as CLK1108 or CLK2109. The flip-flops 104, shown apart from the circuit 102 for illustrative purposes only, will each, upon receiving a triggering clock edge, store a value and hold the value on its respective output until a next triggering clock edge is received. Therefore the flip-flops of circuit 102 collectively represent the state of the circuit: at any time when the clocks are stopped, the flip-flops will maintain the state of the circuit.
By taking advantage of the state-machine nature of the circuit, the state of the circuit 102 can be controlled for test purposes by placing known values into the flip-flops 104. Similarly, the state of the circuit can also be observed by reading the values held in the flip-flops after the circuit has been run. In order to control and observe the values held in flip-flops 104 of the circuit 102, the flip-flops 104 are, in addition to their regular circuit connections represented by lines 112 and 114, coupled to one another in a daisy-chain fashion, i.e., the output of one flip-flop is coupled to the input of the next flip-flop, as generally shown in FIG. 1A. Furthermore, clock steering logic, such as multiplexer 111, is frequently inserted so that all testing and shifting can be effected with one clock signal. To test logic circuit 102, the regular xe2x80x9cmission modexe2x80x9d operation of circuit 102 is stopped and a series of stimulus values are shifted into flip-flops 104, via the daisy-chain, so that each flip-flop in logic circuit 102 has a known value. Stimulus values are shifted in by applying the stimulus values one at a time to the input 106 of the first flip-flop in the daisy-chain and running the circuit clock 108 (coupled to the clock input of each flip-flop 104) to propagate the values through the daisy-chain. After the flip-flops 104 have each received a known test value, the circuit 102 is then exercised (run normally) for a brief period, e.g., one clock cycle, and then stopped. The state of the circuit resulting from its being run is captured in flip-flops 104. The resulting values are then shifted out of the flip-flops 104, by again running the clock 108 and reading the values at the output 110 of the last flip-flop in the daisy-chain.
More specifically, to implement scan-type testing, typically one of two techniques is used: mux-based scan or clock-based scan. xe2x80x9cMux-based scanxe2x80x9d is the more commonly used technique and is described with reference to the block diagram of FIG. 2. Clock-based scan will be described with reference to FIG. 3.
As shown in FIG. 2, for each flip-flop 104n in the logic circuit 102, (where flip-flops 104 are shown apart from circuit 102 for illustrative purposes only) a 2-input multiplexor 212n is placed at the D-input of each respective flip-flop 104n. One input, e.g., the 0 input, for each multiplexor 212n receives the regular connection 114 from the logic 102 that would otherwise go directly into the D-input but for the multiplexor 212n. The second input, e.g., the 1 input, of each multiplexor 212n is coupled to the output of a flip-flop 104n+1, thereby daisy-chaining the flip-flops. As shown in FIG. 2, the Q-output of flip-flop 1042 is coupled to the 1-input of multiplexor 2121, and the Q-output of flip-flop 1041 would be coupled to another multiplexor 2120 (not shown). The 1-input to multiplexor 2122 would be received from the Q-output of flip-flop 1043 (not shown). A circuit clock line (CLK) 108 is coupled to each of the flip-flops 104n as it would be without inclusion of multiplexors 212n. A SHIFT signal 214 is coupled to the select input of each of the multiplexors 212n. When SHIFT 214 is a logical low, the circuit operates normally, as if the multiplexors were not present. Such normal circuit operation can be used for regular mission mode operation as well as for exercising circuitry during test modes. When SHIFT is a logical high, the circuit is placed in a xe2x80x9cshift modexe2x80x9d of operation and test data (stimulus or result values) is shifted into or out of flip-flops 104n by application of a clock signal on CLK 108.
In FIG. 2, to test circuit 102, the circuit 102 is first placed in shift mode by placing a logical high signal on SHIFT 214. The clock signal on CLK 108 is run in a controlled manner while stimulus values are shifted into the flip-flops 104. Once stimulus values are in place, SHIFT 214 is brought to a logical low. The clock signal on CLK 108 is run but controlled to ensure that only a limited number of clock cycles are run, e.g., one clock cycle. Resulting values are then captured in the flip-flops 104n by operation of the last clock edge in this test sequence, also sometimes referred to as a xe2x80x9ccapture clock.xe2x80x9d SHIFT is then brought to a logical high, re-entering shift mode, and a signal on CLK 108 is applied to allow the captured data to be shifted out of the flip-flops 104n.
While the above testing method is useful as described for detecting SAFs, mux-based scan can also be used to test for delay faults. To do so, test data would be shifted into the flip-flops 104n as described above. Then two clock edgesxe2x80x94xe2x80x94xe2x80x9ca launch clockxe2x80x9d and xe2x80x9ca capture clockxe2x80x9dxe2x80x94are applied on CLK 108 with controlled timing between them. The xe2x80x9claunch clockxe2x80x9d is the clock edge that places the circuit in a state ready for test. In delay fault testing, the first clock edge that occurs after the stimulus data is finally positioned in flip-flops 104 is the launch clock, while in the SAF testing scenario described above, the launch clock would essentially be the last clock edge to occur in shift mode. The xe2x80x9ccapture clockxe2x80x9d is the clock edge at which resulting values are captured in the flip-flops 104, and is similar in both delay fault and SAF testing. After the launch clock and the capture clock have been applied, data is shifted out of the flip-flops 104n as described above. If the captured data does not correspond to that expected, then a delay fault may be detected.
The flip-flops already present in the user""s circuit design are used for testing when using a mux-based scan technique, although each flip-flop in logic circuit 102 is essentially replaced with a multiplexor/flip-flop combination to enable daisy-chaining. Nonetheless, the flip-flops present in the user""s logic circuit 102 will often be insufficient to fully test the circuit 102 and additional flip-flop/multiplexor circuitry will need to be added at various points in the design to achieve adequate fault coverage.
Moreover, there are many xe2x80x9cdesign-for-testxe2x80x9d rules (DFT rules) that have become generally known and used in designing user-designed circuits as a direct consequence of mux-based scan in order to avoid problems during testing. These DFT rules include the following:
Circuits should preferably not be designed to include falling-edge triggered flip-flops. Otherwise, some flip-flops would be clocked on the rising edge of the circuit clock, and some would be clocked on the falling edge. In such a situation, during a test data shift in, some of the flip-flops may not receive appropriate stimulus values and to avoid this situation extra test flip-flops may need to be included in the daisy-chain.
Clocks should only be designed to be coupled to clock pins and not to the D-input of a flip-flop or a gate that ultimately is coupled to the D-input of a flip-flop. Otherwise, setup and hold time violations may occur during test mode and the circuit will not reliably capture response values.
The Q-output of a flip-flop should not be directly or indirectly (e.g., through combinational logic or drivers) coupled to the clock input of another flip-flop (such as in a Johnson counter), as that clock-input will not be adequately controllable during testing. More generally, clock inputs throughout the circuit must be controllable for testing the circuit.
All gates through which the clock passes must also be controlled during testing to allow the clock to pass uninfluenced by other values during test value shifting. For instance, if the clock signal is applied to the first input of a 2-input AND-gate, where the AND-gate output is applied to the clock input of a flip-flop, then the second input to the AND-gate must be held to a logical high during a test value shift.
All asynchronous clear and reset pins must be gated so they can be prevented from interfering with shift mode.
Other DFT rules are also commonly known. Many of these DFT rules are a direct result of the fact that testing, e.g., controlling and observing values, can only be done with static patterns (logical high and logical low values)xe2x80x94clock edge transitions can not be generated.
Thus, not only does mux-based scan add additional circuitry (e.g., muxes and additional flip-flops) to the circuit, taking up considerable real estate on an integrated circuit, but the DFT rules, which have often developed as a result of the limitations of mux-based scan, have placed considerable limits on the design of the circuit, all to simply allow testing of the circuit.
A second type of scan technique is xe2x80x9cclock-based scanxe2x80x9d, described with reference to the block diagram of FIG. 3. Rather than replacing each flip-flop in the logic circuit 102 with a mux/flip-flop combination as in mux-based scan, the flip-flops 104n in the logic design 102 are replaced with a dual interface flip-flop 304 shown in FIG. 3. Flip-flop 304 is composed of one flip-flop having two interfaces: one interface is shown in lower portion 310 and one interface is shown in the upper portion 312 of flip-flop 304. When placed in a circuit 102, the inputs and outputs (D, Q, CLK) of lower interface 310 are coupled to receive signals used for normal operation (mission mode). The inputs and outputs (TD, TQ) of upper interface 312 are coupled with the upper interface of other flip-flops 304 to form a daisy-chain, and TCLK is coupled to receive a test clock signal, which can be distinct from the regular circuit clock (the xe2x80x9cuser clockxe2x80x9d) coupled to CLK.
A signal input to SHIFT 314 indicates whether the upper interface or the lower interface should be active. When the signal coupled to the SHIFT input 314 is a logical low, the upper interface 312 maybe inactive while the lower interface 310 must be active. Thus, when the signal on SHIFT 314 is low, the circuit 102 behaves in mission mode. When the signal on SHIFT 314 is a logical high, the lower interface 310 must be inactive and the upper interface 312 must be active. Stimulus values are shifted into the respective flip-flops 304 via the daisy chained upper-interfaces 312, using TCLK to control the shift mode. Once stimulus values are in place, the circuit will be run in test mode for a controlled time period (i.e., SHIFT receives a logical low), after which SHIFT is again asserted high to enable captured values to be shifted out under control of TCLK. As will be understood by those of skill in the art, clock-based scan can easily mimic mux-based scan. As is also known in the art, device 304 may be a latch having two interfaces (one for mission and test modes and one for shift mode) rather than a flip-flop.
Clock-based scan is advantageous over mux-based scan in that clock-based scan has fewer DFT rules associated with it. Since a separate interface and test clock are used for testing, most clock related DFT rules will no longer need to be followed when designing the underlying circuit. Nonetheless, clock-based scan tends to be more expensive than mux-based scan, causing it to be used less frequently than mux-based scan. In addition, even in clock-based scan, flip-flops will need to be added into the user-designed circuit in places where those present in the user-designed circuit are insufficient for test purposes.
Thus, although scan techniques are widely used to test integrated circuits, they are replete with limitations. Not only do scan techniques add a considerable number of devices to the design of the circuit (e.g., muxes and/or flip-flops), taking up considerable real estate, but use of such additional circuitry will limit the availability of circuitry that could otherwise be used for regular circuit operation. In other words, in a gate array, to insert a multiplexor and/or flip-flop into the circuit for test purposes, various function blocks, or portions thereof, will be sacrificed for testing purposes and become unusable for implementing the logic to be used for the regular (non-test) portion of the circuit. Moreover, when using scan techniques, and mux-based scan in particular, numerous DFT rules will need to be followed just to allow testing of the circuit, limiting the flexibility of circuit design or considerable additional expense will be required to include appropriate dual-interface devices for clock-based scan.
To make it even more difficult to design integrated circuits, test circuitry cannot be inserted into the circuit until the circuit design is substantially complete. More specifically, the knowledge of where the circuit""s flip-flops and/or latches are located in the circuit and how they are connected is critical to the ability to insert additional appropriate test circuitry. Typically, once the circuit is designed, then the design is modified for testing purposes, replacing flip-flops in the circuit with a multiplexor/flip-flop combination or a dual-interface flip-flop. Then the circuit must be further analyzed to determine if portions of the circuit need to have additional flip-flops or clock steering logic inserted to adequately test the circuit. Thus, test circuitry can only be added with prior knowledge on the part of the IC designer of the completed circuit design. If space is an issue on the IC, the user""s circuit may need to be redesigned to accommodate the test structures.
In addition, the nature of scan requires that once stimulus data is placed in the respective flip-flops, the entire circuit must be exercised simultaneously. Hence, considerable computational effort will have to be made in designing test vectors in order to ensure that appropriate stimulus values will be placed in the circuit as well as to ensure that all parts of the circuit that can influence resulting captured values have been accounted for. Further, having to exercise the entire circuit simultaneously makes faults more difficult to isolate as the source of the problem may not be immediately apparent.
Therefore, a gate array design that inexpensively (in terms of real estate and other resources) implements the testing of a circuit implemented by the gate array without prior knowledge of the circuit, permits full testing of the circuit without complex DFT rules, and allows portions of the circuit to be exercised in isolation from the rest of the circuit, saving considerable time and computational effort, would represent an advancement in the art.
A system for testing an integrated circuit, and particularly a gate array, is disclosed which overcomes the deficiencies and limitations discussed above. In general, a system in accordance with the invention includes an array of logic blocks, where the logic blocks include a predesigned arrangement of devices and where the logic blocks are couplable to form a user-designed circuit, e.g., by customizing routing. Within the logic blocks and prior to any knowledge of the user-designed circuit, the predesigned arrangement of devices includes logic to enable testing of the user-designed circuit to be later formed. The logic to enable testing allows the logic blocks to be selectable to operate in a freeze mode, a mode unlike the modes of conventional scan, or to operate in normal mode. When selected to operate in a normal mode of operation, each of the logic blocks forms part of the user-designed circuit (when customized), and may operate to perform a sequential logic function, a combinational logic function, a memory logic function, or other function. When selected to operate in freeze mode, the logic blocks operate together as a series of daisy-chained master-slave flip-flops, nonresponsive to user signals, regardless of the underlying function performed by each of the logic blocks in its respective normal mode of operation, as dictated by the user-designed circuit.
Also advantageous over conventional scan, the logic blocks in the array are further predesigned so that each logic block is equipped with addressable mode control, allowing each logic block to be individually selected to exercise (operate in normal mode) while other logic blocks simultaneously remain frozen, driving out stimulus data values.
To test a user-designed circuit, all the logic blocks are first selected, via addressable mode control, to be frozen, thereby forming daisy-chained flip-flops. Stimulus values are shifted into the flip-flops via the daisy-chain. Once shifting has completed, certain isolated and/or nonadjacent logic blocks, selected by addressable mode control, are exercised (i.e., permitted to operate in a normal mode of operation) to verify their operation. Thereafter, all logic blocks are again frozen and then captured data is shifted out of the array. Such a method of testing the user-designed circuit is referred to herein as partition test. Moreover, as discussed previously, such a method of isolated testing is not generally achievable with conventional techniques.
Another method of testing the operation of a user-designed circuit in accordance with the invention is xe2x80x9cscan-emulationxe2x80x9d testing. To perform scan-emulation testing, first all logic blocks are frozen, via addressable mode control, and then stimulus values are shifted into the logic blocks via the daisy-chained flip-flops. Then all logic blocks are selected, also via addressable mode control, to operate in normal mode. Thereafter, all logic blocks are again selected to freeze. Data captured in the frozen logic blocks (i.e., in the daisy-chained flip-flops) is then shifted out of the array.
During shifting, in addition to the logic blocks each behaving as a flip-flop, the master latch and the slave latch of each flip-flop are capable of latching independent data values, allowing independent control and observation of each latch in the respective flip-flops. To do so, the test clock is independently enabled and disabled to each latch.
Implementing predesigned logic blocks in accordance with the invention permits fully testing a gate array without the user (IC designer) having to insert test structures into the user-designed circuit unlike in conventional scan techniques. Moreover, circuitry to enable testing in accordance with the invention is placed in logic blocks prior to any knowledge of the user-designed circuit, and therefore testing of the user-designed circuit does not depend on placement of flip-flops or other sequential logic in the user-designed circuit.
In addition, a logic block in accordance with the invention is used for dual purposes: (1) during test, it can be selected in an addressable manner to freeze, driving out stimulus data, or (2) the same circuitry that can drive out stimulus data, when not selected to be frozen, will perform in normal mode whatever function is dictated by the user-designed circuit, including combinational, sequential, or other functions. Thus, only a minimal number of devices need be included in the predesigned logic blocks prior to customization by a user to enable test.
Further, logic blocks predesigned in accordance with the invention impose few limitations on designers of user-designed circuits in the form of DFT rules. Thus, using an array including logic blocks in accordance with the invention will have high flexibility for the user in terms of user circuit design. Moreover, because the logic blocks are equipped with addressable mode control, small portions of a user-designed circuit can be tested in isolation. Still, a scan-emulation method of testing can be used with logic blocks predesigned in accordance with the invention for those design engineers who prefer that technique.
More specific details of test circuitry in accordance with the invention are described below.